SNUG India 2006 May 24, 2006

Conference at a Glance

Thursday, May 25 - Session Abstracts Session Abstracts

Time Description
7:45 - 9:15 Breakfast / Registration
9:15 - 10:15 Keynote Address - Aart de Geus
Chairman of the Board and CEO, Synopsys, Inc.
10:15 - 10:45 Customer Keynote Address - Nagendra Cherukupalli
VP Asia Pacific Design Centers and Chip Integration, Cypress Semiconductor
"Designing Winning Products"
10:45 - 11:30 Corporate Sponsor Presentation - Keith Clarke
VP Technical Marketing, ARM
"Systems to Silicon - a collaborative approach"
11:30 - 11:45 Coffee Break

Track 1
Physical Design and
Sign-off

Track 2
Synthesis and Test

Track 3
Verification
11:45 - 12:15 QoR Benchmark with ICC & PC on 65nm Design Implementation of Power Aware Synthesis Flow for Multi-million Power Complexed SoCs ABV using SystemVerilog
12:15 - 12:45 Reliability Issues - Electro-Migration/IR Drop Analysis using PrimeRail A TCL-Based Functional AUTO ECO Flow Configuration Coverage Model "Automation" in Functional Verification
12:45 - 13:15 Comparative Study of Via Configurable Routing & Regular ASIC Routing Enhanced Gate Level Clock Domain Crossing Analysis Using PT/DC Hitting Bugs Through Assertions in Memory Controllers
13:15 - 14:00 Lunch
14:00 - 14:30 Evaluating the Accuracy & Requirements of a Sign-off Crosstalk Noise Analysis Tool DFT for Mixed-signal ASIC Vera-Based Configurable Verification Environment for Reconfigurable VLIW Processors
14:30 - 15:00 Solving Transition, Capacitance, Crosstalk, Setup & Hold Violations Efficiently in a PT-SI Environment Simpler Diagnosis of Deterministic BIST Verifying a Highly Configurable IP
15:00 - 15:30 Complexities in Timing Analysis - Managing Uncertainty A Novel Method to Reduce Test Time Using DFT Compiler MAX Anatomy of Reuseable Verification IP in a VMM World
15:30 - 15:45 Coffee Break
15:45 - 16:15 Design of Ultra Low Power SRAM Improving Transition Fault Coverage Through the Indentification of Redundant Transition Faults SoC Verification: Challenges & Solutions using SystemVerilog
16:15 - 16:45 Timing Aware Metal Fill using Hercules Test Pattern Compression for a 90nm 128MHz SoC using DFT Compiler MAX GUI-Based Complex SoC Verification Environment using TCPIP Socket
16:45 - 17:15 Improving Quality & Development Time of Standard Cell Libraries with Cadabra Fault Simulation on Non-Scan Designs with Delays Memory Design/Behavioral Model and Custom Blocks Verification using Symbolic Simulation
17:15 - 17:30 Break
17:30 - 18:30 Panel Discussion: "Low Power Design - Is it Mainstream or Just for Survival at 65-nm"
18:30 - 18:45 Best Paper Awards & Other Announcements
18:45 - Onwards Survey Collection, Door Gift Distribution, Entertainment, Cocktails, Dinner

Friday, May 26 -- Session Abstracts Session Abstracts
Time Description
8:00 - 9:15 Breakfast / Registration
9:15 - 10:15 Tutorial: Reaching High-Performance Subsystem Design using AMBA? 3 AXI
10:15 - 11:30 Panel Discussion: IC Compiler
11:30 - 11:45 Coffee Break

Track 1
Implementation

Track 2
Implementation
11:45 - 12:30 Tutorial: Design Compiler 2006 Tutorial: Creating Abutted, Hierarchical Floorplans using JupiterXT
12:30 - 13:15 Tutorial: Improving Accuracy with PrimeTime and PrimeTime SI Tutorial: Getting Started with IC Compiler
13:15 - 14:15 Lunch
14:15 - 15:00 Tutorial: Composit Current Source (CCS) Modeling Technology Tutorial: Designing with Synopsys Power Portfolio in Galaxy
15:00 - 15:45 Tutorial: Dynamic Voltage-drop and EM Analysis for Low Power Designs with PrimeRail Tutorial: Galaxy Reference Flow
15:45 - 16:00 Coffee Break
16:00 - 16:45 Tutorial: HSIMplus CircuitCheck and Applications Tutorial: Test Automation in Galaxy
16:45 - Onwards Survey Collection and Door Gift Distribution



Friday, May 26
VERIFICATION SEMINAR
Verification Seminar Abstracts Session Abstracts
Time Description
9:30 - 10:30 SystemVerilog Solution Update
10:30 - 11:00 Architecting a Practical Verification Environment
11:00 - 11:15 Coffee Break
11:15 - 12:00 Continued: Architecting a Practical Verification Environment
12:00 - 13:00 Panel Discussion: State of the Art Verification Technologies
13:00 - 14:00 Lunch
14:00 - 15:15 Tips for Building a Verification Environment
15:15 - 16:15 Best Practices of Functional Coverage
16:15 - 16:30 Coffee Break
16:30 - 17:30 Practical Debugging of Design Assertions
17:30 - 18:30 Mixed-Signal Verification Techniques
18:30 - Onwards Survey Collection and Door Gift Distribution

Official Website: http://www.snug-universal.org/asia/india_schedule.htm